1. Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to in-process testing of self-aligned silicide contacts on polysilicon gate field effect transistors.
2. Background of the Invention and Description of Prior Art
Complimentary metal oxide semiconductor(CMOS) field effect transistor(FET) technology involves the formation and utilization of n-channel FETs(n-MOSFET) and p-channel FETs(p-MOSFET) in combination to form low current, high performance integrated circuits. The complimentary use of n-MOSFETs and p-MOSFETs, typically in the form of a basic inverter device, allows a considerable increase of circuit density of circuit elements by reduction of heat generation. The increase in device density accompanied by the shrinkage of device size has resulted in improved circuit performance and reliability as well as reduced cost. For these reasons CMOS integrated circuits have found widespread use, particularly in digital applications.
FIG. 1 shows a cross section of a typical sub-micron n-MOSFET 40 on the surface of a silicon substrate 20. The silicon substrate 20 is p-type in the region where the n-MOSFET 40 is formed. This silicon wafer itself may be p-type or may have a discrete p-type region called a well. A p-MOSFET is formed in a corresponding n-type substrate region or n-type well. A field oxide isolation(FOX) 22 is formed by the local oxidation of silicon(LOCOS) patterning an island of active silicon whereon the n-MOSFET is then formed. A thin gate oxide 24 is grown by thermal oxidation and a polysilicon layer is deposited and patterned by well known photolithographic procedures to form the gate electrode 26 of the MOSFET.
An n-type dopant, for example, phosphorous or arsenic, is then ion implanted into the exposed silicon surface forming a lightly doped drain (LDD) region 28. The implanted region is self-aligned to the gate electrode 26. Next sidewall structures 30 are formed by a well known technique comprising a low pressure chemical vapor deposition (LPCVD) of an insulative material such as silicon oxide followed by reactive ion etching (RIE). A second implant, heavier than the first, of the same dopant material then forms the source/drain elements 32 of the n-MOSFET.
Referring now to FIG. 2, a layer of refractory metal, usually titanium is blanket deposited over the wafer. A thermal treatment, for example by rapid thermal processing(RTP), causes the portions of the titanium in contact with silicon to react and form titanium silicide (TiSi.sub.2). Portions of the titanium layer over oxide such as the field isolation 22 and the sidewall spacers 30 do not react, providing the temperature of the RTP is sufficiently low, for example around 650.degree. C. Subsequent chemical dissolution of the un-reacted titanium, for example in an aqueous etchant containing H.sub.2 O.sub.2 and NH.sub.4 OH, leaves TiSi.sub.2 34 over the source/drain regions 32 and also 36 over the polysilicon gate electrode 26.
When the dimensions of the devices shrink into the sub half-micron range, problems begin to appear in this conventional process. In particular, as the devices become smaller, the source/drain regions 32 become shallower and silicide induced damage to the subjacent junctions, such as silicide spiking and junction leakage is likely to occur. In addition, the sidewall spacers 30 also shrink with device miniaturization and silicide bridging of occurs between the source/drain regions and the polysilicon gate electrode.
These various silicide related failure modes are primarily related to parametric abnormalities rather than defects. It is therefore beneficial to be able to detect and identify the causes of these various failure mechanisms in a timely fashion by the use of in-process testing procedures. Thereby defective wafers and/or jobs may be detected at an opportune time and remedial action may be taken with minimal product loss. Because electrical measurements on in-process integrated circuit product structures cannot be made, appropriately designed test structures are needed to further pinpoint the cause of the aberration.
Test structures for in process testing are generally formed either on test wafers or in unused regions of product wafers. The most cost effective placement of test structures in the saw kerf region of product wafers although this is not always possible. Hieber, et.al. U.S. Pat. No. 4,592,921 determine the electrical resistance of metal films during sputter deposition by performing in-situ measurements on a separate reference substrate which is moved alternately with production substrates under the sputtering targets.
Casowitz, et.al., U.S. Pat. No. 4,100,486 cites a test structure for in process measurement of mask defects or random particulate defects which bring about imperfections in diffused regions. The test structure comprising a serpentine stripe is patterned in an oxide layer overlying a silicon surface. After subjecting the exposed silicon to a diffusion process, a layer of platinum is deposited on the wafer. The layer is thermally annealed to form platinum silicide where it contacts the silicon on the serpentine stripe. Excess platinum is then removed by aqueous etching. The platinum silicide lowers the resistance of the stripe enabling resistance measurements by probing the stripe. Opens and shorts in the stripe caused by the presence of defects are located by means of probe testing at various locations on the stripe.
Hsu, et.al., U.S. Pat. No. 5,451,529 uses an insulated metal silicide layer to determine ion implantation dosage by measuring the change in sheet resistance of the test layer caused by implantation damage. Liu, et.al., U.S. Pat. No. 5,637,186 cite test structures and methods for measuring critical dimensions of integrated circuit patterns. Trudell, U.S. Pat. No. 4,305,760 cites a method for avoiding exposure of contact regions of the silicon substrate to a polysilicon etch, thereby reducing junction leakage current by eliminating the damage normally caused by this etch.